This invention generally relates to microprocessors, and more specifically to improvements in interface signaling between modules, systems, and methods of making.
Microprocessors are general purpose processors which provide high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved.
Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in applications such as mobile telecommunications, but not exclusively, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible.
To further improve performance of a digital system, two or more processors can be interconnected. For example, a DSP may be interconnected with a general purpose processor in a digital system. The DSP performs numeric intensive signal processing algorithms while the general purpose processor manages overall control flow. The two processors communicate and transfer data for signal processing via shared memory. Each processor may be in a different clock domain which requires that each processor synchronize control signals received from the other processor to the clock signal in the local clock domain so that well known problems of runt pulses and metastable anomalies are avoided. Synchronization generally requires several clocked latch stages, so that extra time is required in each handshake cycle between the processors in different clock domains.
It has now been determined that performance of a handshake operation between modules in different clock domains can be improved by performing at least part of the handshake asynchronously within an interface circuit of the modules. Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims. The present invention is directed to improving the performance of processors, such as for example, but not exclusively, digital signal processors.
In accordance with a first aspect of the invention, there is provided a digital system having an internal circuit. An interface circuit is connected to the internal circuit, the interface circuit having a first input for receiving a first signal from a remote source and an output for sending a second signal to a remote destination in response to the first signal. The interface circuit is operable to immediately set the second signal to a first state in a glitchless manner in response to a signal edge in the first signal, and to set the second signal to a second state in a glitchless manner in response to the internal circuit.
According to another aspect of the invention, the interface circuit has a second input for receiving a third signal. The interface circuit is operable to selectively set the second signal to the first state in response to either a rising edge in the first signal or a falling edge in the first signal as selected by the third signal.